Thermal, power and signal integrity requirements can present challenges when on devices that operate within harsh environments. Component integration, paired with a growing complexity of the package architectures, larger form factors and higher interconnection densities increase the risk of in-field failures. Over powering or over heating of a device can have serious consequences including internal package failure, down-stream device errors and second level interconnect solder joint failures. Soldering residues are more problematic, and if not understood, can result in both intermittent and complete device failure.
This conference tackles the challenges and best practices for building reliable electronic devices that will perform to design standards when used in harsh environments. Specific topics include building reliable high density assemblies, power electronics, electric hybrids, product assembly challenges, cleaning, coating, process control, and monitoring and tracking production hardware. Challenging areas such as high temperature soldering, solder material advances, and new standards are presented.
Keynote Presentation
The Remarkable Return of Post-Reflow Cleaning as a
Mainstream Process to Improve Reliability
Keynote Abstract
Electronics in Harsh Environments Conference
By Mike Konrad
Founder/CEO Aqueous Technologies
Cleaning post-reflow circuit assemblies, once a mainstream process, was replaced by many assemblers via the adoption of no-clean flux in the early 1990s. Miniaturization and many other factors have contributed to the re-adoption of cleaning making it once again a mainstream process. Today, it is a recognized best-practice to clean post-reflow circuit assemblies designed for high-reliability applications.
There has been a multitude of changes to materials and assembly designs, climactic in use environments, and reliability expectations that have driven the move to restore a cleaning process. The decision to clean circuit assemblies is based on the assembly's residue tolerance. Modern circuit assemblies have the lowest level of residue tolerance in the history of electronics.
Presentation Topics Include:
The Age of No-Clean Fluxes and the Effect on Circuit Assemblies:
The context in which much of the electronic assembly industry chose to abandon cleaning in favor of a no-clean process. What’s changed since that fateful decision?
The Progression Toward Miniaturization, IOT, and Increased Reliability Expectations:
Factors influencing the decision to clean circuit assemblies.
Modern Residue-Related Failure Mechanisms:
Electro-chemical migration takes at least three forms, dendritic growth, parasitic electrical leakage, and CAF (conductive anodic filament). All three ECM manifestations will be discussed.
Beyond ECM
Additional reasons for cleaning post-reflow circuit assemblies beyond ECM mitigation.
Harsh Environments and Other Factors Influencing Reliability:
Many assemblies are functioning in harsh environments. What exactly is the definition of a harsh environment? We’ll discuss how harsh environments decrease a circuit assembly’s tolerance for residues. The explosion of connect devices, many of which are class 1 devices, are subjected to harsh environments and are experiencing field failures in historic numbers.
Cleaning Best Practices:
If cleaning is to be performed, it must be performed thoroughly. A poor cleaning process is a failed cleaning process and will result in rapid failures. We’ll review the cost of cleaning (and not cleaning) and other factors to consider when choosing a cleaning process.
New IPC Cleanliness Testing and Process Monitoring Requirements
IPC has recently changed the methods in which circuit assemblies are considered clean and reliable through a required objective evidence protocol. Gone are pre-established contamination limits. The new objective evidence and process monitoring requirements will be reviewed.
Reflow Profiles and the Effect on Surface Insulation Resistance (SIR) Test Results
Results of a DOE outlining the effects on SIR test results when the peak reflow temperature drifts by single-digit percentages.
New Cleanliness Quantification Standards (IPC J-STD001-H):
IPC’s new J-STD001H is a game changer. The previously recognized cleanliness pass/fail standard has been replaced with a new “Objective Evidence” and Process Monitoring requirement. The new IPC cleanliness quantification requirements and detailed instructions on how to comply will be presented.
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Full Conference Schedule: